Among nonvolatile semiconductor memory devices capable of being electrically programmed, erased and read, NOR flash memory devices may be particularly advantageous because they typically provide for high-frequency operations in programming and reading data.
FIG. 1 is a cross-sectional diagram of a conventional flash memory cell. The flash memory cell is constructed of source and drain regions, 3 and 4, formed of N+ impurities in a P-type semiconductor substrate 2, with a channel region interposed therebetween, a floating gate 6 over the channel region with a thin insulation film less than 100 Å interposed between the floating gate 6 and the channel region. A control gate 8 is isolated from the floating gate 6 with an insulation film 9 interposed between them. Voltage terminals Vs, Vg, Vd, and Vb are provided for supplying voltages while programming, erasing, or reading data and are connected to the source region 3, the drain region 4, the control gate 8, and the semiconductor substrate 2, respectively.
The flash memory cell is programmed by the effect of hot electron injection towards the floating gate from the channel region adjacent to the drain region 4. The electron injection is carried out with the bias condition that the source region 3 and the P-type semiconductor substrate 2 are grounded, a high voltage, e.g., 10V, is applied to the control gate 8, and a voltage of 5˜6V to induce hot electrons is applied to the drain region. If the flash memory cell is programmed by applying such voltages, negative charge (electrons) accumulates in the floating gate 6. The negative charge accumulated in the floating gate increases a threshold voltage of the programmed flash memory cell during a read operation.
In an erase operation, the flash memory cell is erased by the Fowler-Nordheim (F-N) tunneling effect to the control gate 6 from the semiconductor substrate (i.e., bulk) 2. The F-N tunneling is provided by a negative high voltage of −10V being applied to the control gate 8 and a positive voltage of 5V being established between the bulk region and the control gate 8 to induce the F-N tunneling. Under such conditions, the drain region 4 is in a high impedance state (e.g., a floating state) in order to maximize the effectiveness of the erase operation. When the bias voltages according to the erase operation are applied to the corresponding voltage terminals Vg, Vd, Vs, and Vb, an electric field is strengthened between the control gate 8 and the bulk region (i.e., the substrate 2), which enables the F-N tunneling effect to discharge the negative charges to the source region 3 from the floating gate 6. The F-N tunneling may be induced by an electric field of 6˜7MV/cm, which is possible because the thin insulation film of under 100 Å is interposed between the floating gate 6 and the bulk region 2.
In a conventional flash memory device structure, as each bulk region includes a plurality of memory cells. The memory cells in each bulk region are erased as a group. The size of the groups that are erased is, typically, determined by division of the semiconductor bulk material into regions. For example the group or unit of memory cells that are all erased in an erase operation may be referred to as a sector of, for example, 64 Kb.
The flash memory cell has a low threshold voltage after the erase operation and forms a current path between the drain region 3 and the source region 4 in response to a voltage supplied to the control gate 8 during a read operation. Thus, the flash memory cell is detected as an on-cell if it has its threshold voltage in the range of 1˜3V.
After completing the programming and erase operations, it may be necessary to detect whether the operations have been successfully completed, i.e., program and/or erase verification.
FIG. 2 shows variations of cell threshold voltages in accordance with programming and erasing operations in a flash memory device. As illustrated in FIG. 2, the NOR flash memory device is adjusted to have a threshold voltage of 6˜8V when programmed and a threshold voltage of 1˜3V when erased. The erase operation is carried out until the threshold voltage is established in the range of 1˜3V. However, if an erased memory cell has a threshold voltage of 4V after a first erase operation and the threshold voltage decreases by a predetermined amount with each erase operation, a subsequent erase operation may result in the memory cell having a threshold voltage under 1V. In such a case, the threshold voltage thereof is increased. The case where a flash memory cell has been erased and results in a threshold voltage less than 1V is referred to as an over-erased state, and the lowered threshold voltage is increased by way of an erasing repair process.
As discussed above, there is a need to verify if a flash memory cell has been programmed or erased in order to assure the results of the programming or erasing operation. From the verifying operation, under-programmed memory cells can be completely programmed by further carrying out the programming operation and under-erased or over-erased memory cells can be adjusted to correct insufficient threshold voltages.